1. Field of the Invention
The present invention is related to internal integrated circuit (IC) delay measurement circuits, and more particularly to a critical path monitoring circuit having a data output with selectable operating modes.
2. Description of Related Art
Process, voltage, temperature (PVT), e.g., voltage and temperature changes due to workload, as well as other noise sources cause timing variation within an IC design, making it necessary to provide timing margins that compromise the potential performance of designs. For example, in a processor core, the maximum frequency of the processor clock is dictated by the delay of a critical path within the processor, i.e., a path that, at the present operating temperature and voltage, will cause the processor to fail when the frequency of the processor clock is raised above a particular clock frequency. The critical path may be a single critical path for all operating conditions, or the critical path may change, for example, at different operating temperatures of the IC.
Critical path monitor (CPM) circuits have been implemented that simulate the critical path and provide information regarding the critical path delay of a processor or other IC. CPMs may synthesize critical path timing through such delay elements as wired interconnects within the IC and/or logic gates of the IC. CPMs can provide information to a phase-locked loop that generates the processor clock to provide real-time feedback of variations in the critical path delay, e.g., variation of the critical path delay with dynamic changes in the power supply voltage at particular locations within the IC. Although some CPMs generate a real-time average of the critical path delay, the CPMs may not provide other information useful for effective clock-frequency management and/or design evaluation. Further, as the sensitivity of the CPM is increased, errors due to circuit metastability or measurement circuit timing margins may cause error in the CPM measurement results.
Therefore, it would be desirable to provide a critical path monitoring circuit that can provide real-time delay measurement information in addition to processed indications of critical path delay. It would further be desirable to provide a CPM having correction that removes error in the measurement results.